Semiconductor device and fabrication method thereof

ABSTRACT

A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending along a first direction and a vertical fin structure extending along a second direction. The substrate has a first region and a second region. A portion of the horizontal fin structure and the vertical fin structure are disposed in the first region, and the electrical contact structure directly covers the horizontal fin structure and the vertical fin structure within the first region. The gate structure partially overlaps the horizontal fin structure within the second region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to the field of semiconductordevices, and more particularly, to a structure within a well pick-upregion of a semiconductor device and a fabrication method thereof.

2. Description of the Prior Art

With the trend in the industry being towards scaling down the size offield effect transistors (FETs), three-dimensional or non-planartransistor technology, such as fin field effect transistor technology(FinFET) has been developed to replace conventional planar field effecttransistors.

In current techniques, in order to meet the sub-lithographic features,semiconductor device manufacturers often utilize sidewall image transfer(SIT) technology to form required fin structures. In general, SIT mayinclude the following steps. First, a plurality of dummy patterns isformed on a substrate. Then, spacers are respectively formed on eachsidewall of the dummy patterns through a deposition and an etchingprocess. Subsequently, patterns of the spacers may be transferred to thesubstrate by using the spacers as mask. In this way, a plurality ofparalleled fin structures may be formed in the substrate and thephysical dimensions of these fin structures may be used to define theshape and the width of the carrier channel in the transistors. However,the small surface area of these fin structures often limits the size ofthe contact area between itself and the corresponding electrical contactstructure. Since the contact resistance is inversely proportional to thecontact area, apparent voltage drop often occurs inevitably on theinterface between the fin structures and the electrical contactstructures within the well pick-up region, which is definitely bad forthe electrical performance of the transistors.

In order to overcome the above-mentioned high contact resistance withinthe well pick-up region, there is a need to provide a modifiedsemiconductor device and a fabrication method thereof.

SUMMARY OF THE INVENTION

To this end, the main objective of the invention is to provide asemiconductor device and a fabrication method thereof that can solve theproblems of the conventional techniques.

According to one preferred embodiment of the present invention, asemiconductor device is provided. The semiconductor device includes asubstrate, a first fin structure, an electrical connecting structure anda gate structure. The first fin structure includes at least a horizontalfin structure extending along a first direction and a vertical finstructure extending along a second direction. The substrate has a firstregion and a second region. A portion of the horizontal fin structureand the vertical fin structure are disposed in the first region, and theelectrical connecting structure directly covers the horizontal finstructure and the vertical fin structure within the first region. Thegate structure partially overlaps the horizontal fin structure withinthe second region.

According to another preferred embodiment of the present invention, afabrication method of a semiconductor device is provided and includesthe following steps. First, sacrificial patterns are formed on asubstrate and a space is formed on the sidewalls of each sacrificialpattern. Then, the sacrificial patterns ate removed and patterns of thespacers are transferred into the substrate to form a fin structure. Thefin structure includes a horizontal fin structure extending along afirst direction and a vertical fin structure extending along a seconddirection. Subsequently, a gate structure, source/drain structures, andan electrical connecting structure are formed sequentially on thesubstrate. The gate structure overlaps portions of the horizontal finstructure. The source/drain structures are respectively on each side ofthe gate structure. The electrical connecting structure directly coversthe horizontal fin structure and the vertical fin structure.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 to FIG. 7 are schematic diagrams showing a fabrication method ofsemiconductor structures according to a first preferred embodiment ofthe present invention, wherein:

FIG. 1 is a schematic top view showing a structure at the beginning ofthe fabrication process according to a first preferred embodiment of thepresent invention;

FIG. 2 is a schematic cross-sectional diagram taken along a line A-A′ inFIG. 1;

FIG. 3 is a schematic cross-sectional diagram showing a structure aftera pattern transfer process is carried out and a shallow trench isolationis formed;

FIG. 4 is a schematic top view showing a structure after a gatestructure is formed;

FIG. 5 is a schematic cross-sectional diagram taken along a line A-A′ inFIG. 4;

FIG. 6 is a schematic top view showing a structure after an electricalconnecting structure is formed; and

FIG. 7 is a schematic cross-sectional diagram taken along a line B-B′ inFIG. 6.

FIG. 8 is a schematic top view showing a structure according to a firstmodification of the first preferred embodiment of the present invention.

FIG. 9 is a schematic cross-sectional diagram taken along a line C-C′ inFIG. 8.

FIG. 10 is a schematic top view showing a structure according to asecond modification of the first preferred embodiment of the presentinvention.

FIG. 11 is a schematic top view showing a structure according to a thirdmodification of the first preferred embodiment of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are given toprovide a thorough understanding of the invention. It will, however, beapparent to one skilled in the art that the invention may be practicedwithout these specific details. Furthermore, some well-known systemconfigurations and process steps are not disclosed in detail, as theseshould be well-known to those skilled in the art.

Likewise, the drawings showing embodiments of the apparatus are not toscale and some dimensions are exaggerated for clarity of presentation.Also, where multiple embodiments are disclosed and described as havingsome features in common, like or similar features will usually bedescribed with same reference numerals for ease of illustration anddescription thereof.

Refer to FIG. 1 and FIG. 2, FIG. 1 is a schematic top view showing astructure at the beginning of the fabrication process according to afirst preferred embodiment of the present invention. FIG. 2 is aschematic cross-sectional diagram taken along a line A-A′ in FIG. 1. Inthis stage, a substrate 10 having a plurality of sacrificial patterns 14thereon is provided. The sidewalls of each of the sacrificial patterns14 are covered by a spacer 16 with a loop-shaped appearance. Thesubstrate 10 has a first region and a second region defined thereon,which may be respectively corresponding to a well pick-up region R1 andan active region R2 of the semiconductor device, but not limitedthereto. Each sacrificial pattern 14 may cross both of the well pick-upregion R1 and the active region R2. These sacrificial patterns 14 arearranged to have a first layout pattern 100, such as a matrix layoutpattern respectively arranged along a first direction X and a seconddirection Y. The long axis of each of the sacrificial patterns 14 isparallel to the first direction X, but not limited thereto. Preferably,each sacrificial pattern 14 and each spacer 16 respectively have a firstwidth W1 and a second width W2, and the first width W1 is wider than thesecond width W2.

The above-mentioned substrate 10 is preferably a semiconductorsubstrate, such as a silicon substrate, a silicon germanium or the like,and the substrate is preferably not chosen from a silicon-on-insulator(SOI) substrate. The dielectric layer 12 may be a nitride layer or anoxide layer, such as a silicon nitride layer, a silicon oxide layer orother layer made of suitable dielectric materials, which may be formedthrough a thermal oxidation process, a high density plasma CVD (HPCVD)process or a sub-atmosphere CVD (SACVD) process, but not limitedthereto. Optionally, the dielectric layer may not be formed on thesubstrate according to other preferred embodiments. The sacrificialpatterns 14 may be made of semiconductor materials, such as polysiliconmaterial and may be formed through regular deposition,photolithographic, and etching processes. Because of the limitedcapability of the processing machine, a first width W1 of each of thesacrificial patterns 14 is substantially larger than or equal to theminimum exposure limit of the corresponding photolithography process.The spacers 16 may be made of dielectric materials, such as siliconnitride and may be formed through the following steps. First, adielectric material layer (not shown) is formed to conformallyencapsulate each sacrificial pattern 14 and to cover the dielectriclayer 12. Then, the dielectric material layer can be blanketly etched(etched without mask) into a plurality of spacers 16 which isrespectively on and around the sidewalls of each of the sacrificialpatterns 14. The appearance of these spacers 16 is shown in FIG. 1.Preferably, etching rates on the dielectric layer 12, the sacrificialpatterns 14, and the spacers 16 may be controlled at required values byadjusting the compositions of which.

Please refer to FIG. 3. FIG. 3 is a schematic cross-sectional diagramshowing a structure after an image transfer process is carried out and ashallow trench isolation is formed. The structure shown in FIG. 3corresponds to a line A-A′ in FIG. 1. Referring to FIG. 2 and FIG. 3,the sacrificial patterns 14 within the well pick-up region R1 and theactive region R2 are removed completely so as to only leave spacers 16on the dielectric layer 12. An image transfer process, such as asidewall image transfer (SIT), is carried out subsequently. Through thisprocess, a plurality of loop-shaped patterns defined by the spacers 16may be transferred into the surface of the substrate 10 to thereforeform a plurality of loop-shaped protruding structures 20. Eachprotruding structure 20 has a first height H1, and the patterneddielectric layer 18 and the spacer 16 are stacked thereon from bottom totop.

To put it more concretely, the image transfer process may include aseries of etching processes, for example: first, a regular etchingprocess (dry etching or wet etching) is carried out to remove thesacrificial patterns 14 and only leave the spacers 16 on the dielectriclayer 12. By adjusting etch recipes of these etching processes, theetching rate of the sacrificial patterns 14 may be higher than that ofthe spacers 16 so that only little amount of the spacers 16 is etchedaway during these etching processes. Afterward, by using the spacers 16as etching masks, one or more anisotropic etching process is carried outto sequentially and downwardly etch the dielectric layer 12 and/orportions of the substrate 10. Through these processes, the patternsdefined by the spacers 16 may be transferred into the dielectric layer12 and/or the substrate 10. It is worth noting that, the technical term“image transfer process” throughout the specification includes theconcept of the technical term “sidewall image transfer”, that is to say,the technical term “image transfer process” should be regarded as ageneric concept of the technical term “sidewall image transfer”.

Still refer to FIG. 3 accompanied with FIG. 2. After the image transferprocess is completed, a series of fabrication processes may be carriedout for dielectric layer in sequence, such a deposition process, aplanarization process, and an etching back process, to form a shallowtrench isolation 22 having a first depth D1 around the bottom of each ofthe protruding structures 20. Portions of each of the protrudingstructures 20, also called fin structures 24, may protrude from thesurface of the shallow trench isolation 22 and have a height around 300to 400 angstroms. It is worth noting that, the width of each of thespacers 16 may be trimmed away slightly during the above image transferprocess. Therefore, the width of each of the fin structures 24 may bethinner than the original second width W2 of each corresponding spacer16.

Please refer to FIG. 4 and FIG. 5. FIG. 4 is a schematic top viewshowing a structure after the formation of a gate structure. FIG. 5 is aschematic cross-sectional diagram taken along a line A-A′ in FIG. 4. InFIG. 4 and FIG. 5 accompanied with FIG. 3, each spacer 16 and eachpatterned dielectric layer 18 stacked on the fin structures 24 areremoved through a suitable etching process to expose fin structures 24,such as a first fin structure 24 a, a second fin structure 24 b, a thirdfin structure 24 c and a fourth fin structure 24 d, but not limitedthereto. Preferably, each of the fin structures 24 a, 24 b, 24 c and 24d is across the well pick-up region R1 and the active region R2 and aU-shaped end of each of the fin structures 24 a, 24 b, 24 c and 24 d isdisposed within the well pick-up region R1. In other words, the end ofeach of the fin structures 24 a, 24 b, 24 c and 24 d has two horizontalfin structures 26 a and a vertical fin structure 26 b.

Afterward, other fabrication processes may be carried out. For example,a series of ion implantation processes are performed in sequence so thata well doped region 28 and a well pick-up doped region 30 having a firstconductivity type, such as P type, are formed. The well doped region 28is formed in both the well pick-up region R1 and the active region R2,while the well pick-up doped region 30 is merely formed in the wellpick-up region R1. What is more, the well pick-up doped region 30 may beregarded as a heavily doped region disposed inside the well doped region28. In other words, the doping concentration of the well pick-up dopedregion 30 is higher than that of the well doped region 28. In a nextstep, at least a gate structure 32 is formed in each of the activeregions R2 so as to enable each gate structure 32 to concurrentlydirectly contact with a set of mutually parallel fin structures 24, butnot limited thereto. Accordingly to other embodiments, a set of mutuallyparallel gate structures may be disposed within each active region.Preferably, gate structures 32 may be arranged as shown in FIG. 4 andrespectively encapsulate each fin structure 24. In addition, thestructure of the gate structure 32 at least includes a gate dielectriclayer (not shown), a gate conductive layer (not shown), and a cap layer(not shown) from bottom to top. The sidewalls of each gate structure 32are covered by a gate spacer (not shown). The composition of the gatedielectric layer, the gate conductive layer, and the cap layer mayrespectively correspond to silicon oxide, polycrystalline silicon/metalmaterial, and silicon nitride, but not limited thereto.

Still referring to FIG. 4, a coating and a photolithographic process arecarried out sequentially so as to form a patterned mask layer (notshown) on the substrate 10. The patterned mask layer may expose thestructures, such as the shallow trench isolation 22, the fin structures24 and the gate structure 32, within each of the active regions R2.Afterward, under the coverage of the patterned mask layer, the gatestructure 32, and the gate spacer, an ion implantation process iscarried out so that a source/drain doped region 34 is formed in each finstructure 24 at each side of each gate structure 32. Each source/draindoped region 34 is a heavily doped and may be regarded as a regioninside the well doped region 28. Additionally, the conductivity type ofthe source/drain doped region 34 differs from that of the well dopedregion 28 and the well pick-up doped region 30. That is to say, eachsource/drain doped region 34 has a second conductivity type, such asN-type, according to the present embodiment. Finally, the patterned masklayer is removed.

Please refer to FIG. 6 and FIG. 7. FIG. 6 is a schematic top viewshowing a structure after an electrical connecting structure is formed.FIG. 7 is a schematic cross-sectional diagram taken along a line B-B′ inFIG. 6 Referring to FIG. 6 and FIG. 7, after the removal of thepatterned mask layer, a blanket deposition process is carried out toform an interlayer dielectric 38 on the substrate 10. Subsequently, aplanarization process is implemented on the interlayer dielectric 38 andthe interlayer dielectric 38 may still completely cover each finstructure 24 and each gate structure 32. Then, a plurality of contactholes 40 is formed in the interlayer dielectric 38 through an etchingprocess and portions of the corresponding fin structure 34 may beexposed from the bottom of the contact holes 40. In the subsequentfabrication process, the portions of each fin structures 24 exposed fromthe contact hole 40 may be used as contact regions to be electricallyconnected to an external circuit.

It should be noted that, since a gate first process is adopted in thisembodiment, the conductive material in the gate structure 32 will not bereplaced after the interlayer dielectric 38 is formed, but not limitedthereto. The present invention may also adopt a gate last process, alsocalled replacement metal gate (RMG), so as to replace the conductivematerial in the gate structure. For example, after the formation of theinterlayer dielectric, a polishing process may be carried outcontinuously until the exposure of a top portion of the gate structure,such as the exposure of the cap layer. Then, at least a removing processand a metal deposition process are carried out so as to replace theoriginal conductive material in the gate structure, such aspolycrystalline silicon, with a metal material with relatively highconductivity, such as aluminum, tungsten, copper or the like. In thisway, the gate last process is accomplished.

Still referring to FIG. 6 and FIG. 7, after a plurality of contact holes40 is formed in the interlayer dielectric 38, an electrical contactstructure 42 may then be formed inside each contact hole 40, such as aslot contact structure, to be in direct contact with and cover portionsof each fin structure 24. One feature of the present invention is thatthe electrical contact structure 42 within the well pick-up region R1may not only directly cover the horizontal fin structure 26 a, but alsodirectly cover the vertical fin structure 26 b. To put it moreconcretely, each electrical contact structure 42 within the well pick-upregion R1 may concurrently cover two opposite lateral surfaces 80 a and80 b and top surface 80 c of each horizontal fin structure 26 a and eachvertical fin structure 26 b, which enables its contact area to beincreased and its contact resistance to be reduced. In this structure,if a voltage is applied to the well pick-up region, only a small voltagedrop will occur on the interface between the electrical contactstructure and the horizontal and vertical fin structures. As a result,the voltage can be effectively applied to the well doped region throughthe well pick-up doped region. It should be noted that the electricalcontact structure 42 may include a barrier layer and/or adhesive layer,such as titanium nitride or tantalum nitride, and an electricalconductive layer, such as aluminum, tungsten, copper or other conductivematerials with relatively high conductivity, but not limited thereto.

In addition to the above-mentioned first preferred embodiment, thepresent invention also includes other modified embodiments ofsemiconductor structures. Since structures and fabrication process inthese modified embodiments are substantially similar to those disclosedin the first preferred embodiment, the following paragraphs will focuson the main difference among these embodiments and similar features willusually be described with same reference numerals for ease ofillustration and description thereof.

Please refer to FIG. 8 and FIG. 9. FIG. 8 is a schematic top viewshowing a structure according to a first modification of the firstpreferred embodiment of the present invention. FIG. 9 is a schematiccross-sectional diagram taken along a line C-C′ in FIG. 8. The structureshown in FIG. 8 according to the first modification corresponds to thestructure shown in FIG. 6 according to the first preferred embodiment.The main difference between these two embodiments is that asemiconductor device according to the first modification furtherincludes a plurality of shielding structures 60 used to preventepitaxial layers from growing in specific regions of the fin structures24. At least one of the shielding structures 60 is disposed between thetwo electrical contact structures 42 within the well pick-up region R1,while at least two of the shielding structures 60 are in direct contactwith a set of fin structures 24 within the well pick-up region R1,especially in direct contact with a plurality of horizontal finstructures 26 a, but not limited thereto. Therefore, each electricalcontact structure 42 within the well pick-up region R1 may cover anddirectly contact the corresponding shielding structure 60, but notlimited thereto. Accordingly to other embodiments, the shieldingstructures may also be disposed between the electrical connectingstructures respectively within the well pick-up region and the activeregion so that they may be separated from the electrical connectingstructures. Compared with conventional semiconductor devices, eventhough the shielding structures 60 are disposed on the substrate 10according to the first modification, the existence of the vertical finstructures 26 b within the well pick-up region R1 may enable thesemiconductor device to have relatively low contact resistance and thereduced size of well pick-up region R1. Accordingly, the integrity ofthe semiconductor device is improved.

To put it more concretely, the structure and the fabrication timing ofthe shielding structures 60 according to this first modification may bethe same as that of the gate structure 32 within the active region R2.For example, when the gate structure is formed through the gate firstprocess, each shielding structure 60 may also encapsulate portions ofeach of the fin structures 24. The shielding structure 60 may at leastinclude a dielectric layer 62, an electrical conductive layer 64, and acap layer 66 from bottom to top. Additionally, the composition of thedielectric layer, the electrical conductive layer, and the cap layer maybe respectively corresponding to that of the gate dielectric layer, thegate conductive layer, and the cap layer disclosed in the firstpreferred embodiment, but not limited thereto. A gate last process mayalso be adopted for fabricating the gate structure and/or the shieldingstructure according to the present invention.

In addition to the first modification, the present invention furtherincludes a second modification of the first preferred embodiment. Pleaserefer to FIG. 10. FIG. 10 is a schematic top view showing a structureaccording to a second modification of the first preferred embodiment ofthe present invention. The structure and the fabrication timingaccording to this second modification may be similar to that accordingto the first preferred embodiment. The main difference between these twostructures is that the third fin structure 24 c on the right side of theactive region R2 only has two parallel horizontal fin structures 26 aand has no vertical fin structure 26 b. In contrast, the first, second,and fourth fin structures 24 a, 24 b, and 24 d still have the horizontalfin structures 26 a and the vertical fin structure 26 b. Accordingly,the electrical contact structure 42 disposed on the right side of thewell pick-up region R1 may only directly cover the two parallelhorizontal fin structures 26 a of the third fin structure 24 c. Apartfrom the third fin structure 24 c without the vertical fin structure 26b, the structure and the fabrication processes according to this secondmodification are substantially similar to that shown in FIG. 1 to FIG. 9according to the first preferred embodiment and the first modification.The detailed description of these is therefore omitted for the sake ofclarity.

In addition to the first modification, the present invention furtherincludes a third modification of the first preferred embodiment. Pleaserefer to FIG. 11. FIG. 11 is a schematic top view showing a structureaccording to a third modification of the first preferred embodiment ofthe present invention. The structure and the fabrication processesaccording to this third modification are substantially similar to thataccording to the first preferred embodiment. The main difference betweenthese two embodiments is that the electrical contact structure 42 withinthe well pick-up region R1 directly covers all vertical fin structures26 b of the first to fourth fin structures 24 a, 24 b, 24 c and 24 d.Apart from the electrical contact structure 42 directly covering allvertical fin structure 26 b of the first to fourth fin structures 24 a,24 b, 24 c and 24 d, the structure and the fabrication processesaccording to this third modification are substantially similar to thatshown in FIG. 1 to FIG. 9 according to the first preferred embodimentand the first modification. The detailed description of which istherefore omitted for the sake of clarity.

It should be noted that each of the modifications should not beconstrued in a limiting sense and may be combined with one anotherproperly if required. For example, under a situation that the wellpick-up region includes the shielding structure therein, there may beonly one electrical contact structure disposed within the well pick-upregion to directly contact with all the vertical fin structures in thefirst to fourth fin structures, but not limited thereto.

For the sake of clarity, the horizontal and vertical fin structures 26 aand 26 b disclosed in each of the above-mentioned embodiments are usedas contact regions within the well pick-up region R1. However, thehorizontal and vertical fin structures 26 a and 26 b according to thepresent invention can be not only used within the well pick-up regionR1, but also equivalently applied within other suitable regions. Forexample, the horizontal and vertical fin structures may be applied insource/drain regions of a transistor, or applied in resistor, diodedevice, photosensitive device, bipolar junction transistor (BJT), or thelike.

To summarize, accordingly to embodiments of the present invention, thehorizontal fin structures and the vertical fin structures are disposedwithin the well pick-up region of the semiconductor device. Therefore,the electrical contact structure within the well pick-up region may notonly directly cover the horizontal fin structure, but also directlycover vertical fin structure, which enables the relatively high contactarea and relatively low contact resistance become possible. In thisstructure, if a voltage is applied to the well pick-up region, only asmall voltage drop will occur between the electrical contact structureand the horizontal and vertical fin structures. As a result, the voltagecan be effectively applied to the well doped region through the wellpick-up doped region and the performance of the semiconductor device isimproved.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A semiconductor device comprising: a substrate,having a first region and a second region; a first fin structure,disposed on the substrate, the first fin structure comprising at least ahorizontal fin structure extending along a first direction, and avertical fin structure extending along a second direction, whereinportions of the horizontal fin structure and the vertical fin structureare disposed in the first region; an electrical contact structure,directly covering the horizontal fin structure and the vertical finstructure within the first region; and a gate structure, disposed on thesubstrate, wherein the gate structure partially overlaps the horizontalfin structure within the second region.
 2. The semiconductor deviceaccording to claim 1, wherein the first direction is perpendicular tothe second direction.
 3. The semiconductor device according to claim 1,wherein the first fin structure is a loop structure.
 4. Thesemiconductor device according to claim 1, wherein the first finstructure is a loop structure with an opening.
 5. The semiconductordevice according to claim 1, the first fin structure further comprisinganother horizontal fin structure extending along the first direction,wherein the electrical contact structure is in direct contact with thehorizontal fin structures and the vertical fin structure within thefirst region.
 6. The semiconductor device according to claim 1, whereinthe horizontal fin structure and the vertical fin structure respectivelycomprise two opposite lateral surfaces, and the electrical contactstructure is in direct contact with the lateral surfaces.
 7. Thesemiconductor device according to claim 1, wherein the first region is awell pick-up region and the second region is an active region.
 8. Thesemiconductor device according to claim 7, further comprising a wellpick-up doped region having a first conductivity type and disposedwithin the well pick-up region.
 9. The semiconductor device according toclaim 7, further comprising a source/drain doped region having a secondconductivity type and disposed within the active region.
 10. Thesemiconductor device according to claim 9, wherein the source/draindoped region is disposed within the horizontal fin structure and at oneside the gate structure.
 11. The semiconductor device according to claim1, further comprising a well pick-up doped region and a source/draindoped region respectively disposed within the first region and withinthe second region, wherein the well pick-up doped region has a firstconductivity type, the source/drain doped region has a secondconductivity type, and the first conductivity differs from the secondconductivity type.
 12. The semiconductor device according to claim 1,further comprising a shielding structure covering portions of thehorizontal fin structure, wherein the electrical contact structurecovers portions of the shielding structure.
 13. The semiconductor deviceaccording to claim 1, further comprising: a second fin structure,disposed on the substrate, the second fin structure comprising at leasta horizontal fin structure extending along the first direction and avertical fin structure extending along the second direction, whereinportions of each of the horizontal fin structures and the vertical finstructures are disposed within the first region.
 14. The semiconductordevice according to claim 13, wherein the first direction isperpendicular to the second direction.
 15. The semiconductor deviceaccording to claim 13, wherein the electrical contact structure is indirect contact with horizontal fin structures and the vertical finstructures.
 16. The semiconductor device according to claim 13, whereinthe horizontal fin structure and the vertical fin structure respectivelycomprise two opposite lateral surfaces, and the electrical contactstructure is in direct contact with the lateral surfaces.
 17. Thesemiconductor device according to claim 16, further comprising a wellpick-up doped region and a source/drain doped region respectivelydisposed within the first region and within the second region, whereinthe source/drain doped region is disposed in at least one of thehorizontal fin structures and is disposed at one side of the gatestructure.
 18. The semiconductor device according to claim 17, whereinthe well pick-up doped region has a first conductivity, the source/draindoped region has a second conductivity type, and the first conductivitydiffers from the second conductivity type.
 19. A fabrication method of asemiconductor device, comprising: providing a substrate; forming asacrificial pattern on the substrate; forming a spacer on sidewalls ofthe sacrificial pattern; removing the sacrificial pattern; transferringpatterns of the spacer to the substrate so as to form a fin structure,wherein the fin structure comprises a horizontal fin structure extendingalong a first direction and a vertical fin structure extending along asecond direction; forming a gate structure, overlapping portions of thehorizontal fin structure; forming two source/drain doped regions,respectively being at each side of the gate structure; and forming anelectrical contact structure, directly covering the horizontal finstructure and the vertical fin structure.
 20. The fabrication methodaccording to claim 19, wherein the vertical fin structure exists beforeforming the electrical contact structure.